In digital signal processing, e.g., processing used in digital correlator in digital radio-communications, there is frequently conducted such a calculation that two signals are squared; the two squares are summed; and a square-root of the sum is calculated. Several conventional arithmetic circuits for realizing the above-mentioned square-sum root calculation are be described below:
Conventional circuit I!
A first example of a conventional arithmetic circuit includes (N+1)-bit multipliers for calculating squares of individual input data S.sub.in1 and S.sub.in2, a 2N-bit adder for adding together two squares from respective multiplying circuits and a (2N+1)-bit square-root calculator for calculating a square-root of the square-sum and producing an operation result S.sub.out.
In the thus constructed circuit, inputs Sink and S.sub.in2 of N+1 bits (N bits+Sign bit) each are inputted and squared respectively by (N+1) multipliers. The obtained products (squares of the input values S.sub.in1 and S.sub.in2) are positive, and they each are composed of 2N bits. The squared values S.sub.in1.sup.2 and S.sub.in2.sup.2 are input to the 2N-bit adder whereby two squared values are added together to obtain a (2N+1)-bit sum of S.sub.in1.sup.2 +S.sub.in2.sup.2. The sum is input to the (2N+1)-bit square-root calculator whereby a square-root of a square-sum (S.sub.in1.sup.2 +S.sub.in2.sup.2).sup.1/2 of two inputs S.sub.in1 and S.sub.in2 is calculated to obtain a result S.sub.out. This arithmetic circuit is hereinafter referred to as conventional circuit I!.
Conventional circuit II!
Another example of conventional arithmetic circuit II! calculates a square-root of a square-sum by approximation. This circuit comprises N-bit absolute value calculators for determining absolute values of respective inputs S.sub.in1 and S.sub.in2, a N-bit-absolute comparator for comparing with each other the absolute values .vertline.S.sub.in1 .vertline. and .vertline.S.sub.in2 .vertline., N-bit multiplexers for multiplexing the absolute values by using the comparison result as a selecting signal, a N-bit fixed-value multiplier for multiplying an absolute value by a fixed value and a N-bit adder for adding a product to the output of the N-bit multiplexer and outputting a calculation result S.sub.out. This conventional arithmetic circuit II! approximately determines a square-root of a square-sum of two inputs S.sub.in1 and S.sub.in2 according to the following equation (1). EQU (S.sub.in1.sup.2 +S.sub.in2.sup.2).sup.1/2 .congruent.max{.vertline.S.sub.in1 .vertline.,.vertline.S.sub.in2 .vertline.}+min{.vertline.S.sub.in1 .vertline., .vertline.S.sub.in2 .vertline.}.times.(2.sup.1/2 -1) equation (1)
In the above-mentioned circuit, inputs S.sub.in1 and S.sub.in2 are input to respective N-bit absolute value calculators. The obtained absolute values .vertline.S.sub.in1 .vertline. and .vertline.S.sub.in2 .vertline. are input to a N-bit absolute value comparator whereby they are compared in size. According to the comparison result, the N-bit multiplexer selects the smaller of the two absolute values .vertline.S.sub.in1 .vertline. and .vertline.S.sub.in2 .vertline. and the other N-bit multiplexer selects the larger of the two absolute values .vertline.S.sub.in1 .vertline. and .vertline.S.sub.in2 .vertline..
In this instance, the smaller absolute value (i.e., the output of the N-bit multiplexer) is multiplied by a fixed value (2.sup.1/2 -1) by the fixed-value multiplier and the obtained product is then added to the larger absolute value (i.e., the output of the N-bit multiplexer). The result of an this calculation is outputted as a result S.sub.out of approximate calculation of a square-root of a square-sum of two inputs S.sub.in1 and S.sub.in2.
Conventional circuit III!
Japanese Laid-Open Patent Publication 7-44530 discloses another conventional arithmetic circuit according to the above-described equation (1). In contrast to the conventional arithmetic circuit II! based on the same equation (1), this arithmetic circuit III! approximates in practice the term (2.sup.1/2 -1) by (1+2.sup.2 +2.sup.4 +2.sup.5)/2.sup.7 =0.4140625. This calculation is conducted by a bit-shift. Accordingly, there is no need of using any multiplier, reducing the size of the circuit. This circuit, however, requires a plurality of clock pulses for obtaining the operation result.
Conventional circuit IV!
Similarly to the above-mentioned conventional circuit II!, this arithmetic circuit is intended to approximately calculate a square-root of a square-sum of two inputs. Circuit IV! is composed of N-bit absolute value calculators for determining absolute values of inputs S.sub.in1 and S.sub.in2, a N-bit absolute value comparator for comparing the obtained absolute value .vertline.S.sub.in1 .vertline. with the obtained absolute value .vertline.S.sub.in2 .vertline., N-bit multiplexers to be selected by respective selecting signals according the comparison result, a 1-bit right shifter for shifting the smaller output absolute value of N-bit multiplexers by 1 bit to the right and a N-bit adder for adding the shifting result to the larger output value of the N-bit multiplexers.
The thus constructed conventional arithmetic circuit conducts an approximate calculation of a square-root of a square-sum of two inputs S.sub.in1 and S.sub.in2 according to the following equation (2) (cited from a catalogue of digital matched filter STEL-3340 manufactured by Stanford Telecommunications, Inc.). EQU (S.sub.in1.sup.2 +S.sub.in2.sup.2).sup.1/2 .congruent.max{.vertline.S.sub.in1 .vertline., .vertline.S.sub.in2 .vertline.}+1/2min{.vertline.S.sub.in1 .vertline., .vertline.S.sub.in2 .vertline.} equation (2)
In the circuit, inputs S.sub.in1 and S.sub.in2 are input to the N-bit absolute value calculators respectively. Absolute values .vertline.S.sub.in1 .vertline. and .vertline.S.sub.in2 .vertline. obtained by the N-bit absolute value calculators are input to the N-bit absolute comparator which judges which of two absolute values is larger. According to the judgment, the N-bit multiplexer selects the smaller of the two absolute values .vertline.S.sub.in1 .vertline. and .vertline.S.sub.in2 .vertline. and the other N-bit multiplexer selects the larger.
The smaller absolute value outputted by the N-bit multiplexer is shifted by 1 bit to the right by the 1-bit right shifter. The value obtained by the 1-bit right shifter is then added by the N-bit adder to the larger absolute value outputted by the N-bit multiplexer. This N-bit adder obtains an approximate value S.sub.out of a square-root of a square-sum of two inputs S.sub.in1 and S.sub.in2.
The above-described conventional arithmetic circuits, however, involve the following problems:
The conventional arithmetic circuit I! may have a considerably large size since the number of gates of the multipliers and the square-root calculator is increased in proportion with the squared number of bit number M of input data. Furthermore, the multipliers have a large delay time necessary for adding the multiplying products of each digit by the number of digits and the square-root calculator have a slow speed processor according to the adder with adding steps being a 1/2 of digits and sequential circuit which operates with the clock pulses corresponding to the adding steps.
In comparison with the conventional example I!, the conventional arithmetic circuit II! operates by an approximating method which may have a reduced number of gates, which is proportional to the squared number of bit number M of input data (with a smaller coefficient of squaring the bit number M). However, it is still large in size. With 8 bits, the number of gates of this conventional circuit II! is about 1/2 of that of the conventional circuit I!. The operating speed is higher than that of the conventional circuit I!.
The conventional arithmetic circuit III! may perform, with the further reduced number of gates, the same approximate calculation as the conventional circuit II!, but it still requires a plurality of clock pulses for executing its operation (e.g., 20 and several clock-pulses with the bit number M of 8). Consequently, this method can not be used where the real time processing is required.
The conventional arithmetic circuit IV! uses a further simplified approximate calculation may have the considerably reduced number of gates as compared with the circuits I! and II! to the extent that the number of gates is proportional to the number M of bits (e.g., 1/3 of that of the conventional circuit II! at M=8). This arithmetic circuit requires no multiplier nor square calculator as used in circuit II!. Consequently, it can operate at an increased speed. However, this conventional arithmetic circuit IV! has a large error of approximation and has, therefore, a low accuracy of calculation.
Errors arise from the two approximating operations made by the conventional circuits II! and IV! from the theoretical values when an input S.sub.in1 is changed from 0 to 100 with a input S.sub.in2 fixed at 50. The theoretical values shows that the conventional arithmetic circuit II! of smaller error of approximation has a large size whereas the conventional arithmetic circuit IV! of smaller size has a large error of approximation. Accordingly, both circuits can not be compatible with each other. The conventional arithmetic circuit III! has a small size but requires a plurality of clock pulses for its operation that is unusable for real time data processing.